Sunday, September 30, 2012

The Electronic Quick Change Gear Box, part 2

(continued from part 1)

More about the CPLD

I've said that the CPLD doesn't run a program, yet I talk about programming it.  How is this not double-speak?

The distinction is that a program can be thought of a series of instructions executed by some manner of processor such as an Arduino.  When the processor is started, the program might be loaded from eprom into volatile memory and the processor's instruction pointer set to the appropriate location.  The program runs, the sun shines, and the birds sing.

But for the CPLD, things are different. When I talk about programming it, I'm not talking about creating a sequence of instructions.  Instead, I'm talking about configuring connections between gates that are baked into the CPLD's silicon.


Connecting wires to IC pins is very tedious.  While it would be possible to virtually solder the connections between the CPLD's gates, developers needed something a more efficient and less error-prone way.  Verilog was thus created.  It's a language having elements that should be familiar to almost all programmers.  It includes support for primitive constructs but also support for building and reusing higher level constructs. The web is full of references and Amazon sells many books about Verilog.  Just for a taste, the following is a perfectly valid Verilog program that makes one of the LEDs on my development board flash every second.

01 module demodelay(
02    input CLK,
03    output reg GO
04    );
06    reg[18:0] snooze = 0;
07    always @(posedge CLK) begin
08        snooze = snooze + 1;
09        if (snooze == 500000) begin
10            GO = !GO;
11            snooze = 0;
12            end
13        end
14 endmodule

This isn't so different looking from a normal C or Java program.  Same stuff, different syntax.  Here are the high points.  (Bear in mind, this Verilog module is written so it's easy to explain and understand and does not take advantage of knowledge about what we're really doing, which is configuring hardware.  This module could be written far more efficiently.)

On line 1, we see the name of the module is declared - demodelay.

On line 2, we see the input is something called CLK.  The program has a configuration that ties a 1MHz clock signal to this input.  Thus CLK will transition from low to high 1 million times a second.

On line 3, the output is something called GO.  This is what will drive the LED output.  Note the word 'reg'.  This makes the value persistent.  Once we set the value, it stays that way.

Line 6 shows something that looks like a variable.  It is, after a fashion.  It's 19 bits of persistent storage. Every one of these bits will become a flip-flop or a latch. So here's one difference between Verilog and typical programming languages - In Verilog, we care very much how wide our variables are - these definitions contribute directly to the consumption of the CPLD's resources.  If we were programming in Java, we might just declare 'snooze' to be an int.  When our method was invoked, the JVM would create a stack frame including 32 bits of storage for 'snooze'.  When our method exited, the JVM would reclaim the stack frame.  We wouldn't worry too much about the underlying reality; this is the point of using higher level languages.

Magic begins on line 7.  What this statement means is that whenever CLK (an input) transitions from a low state to a high state (0 to 3.3v, perhaps), the logic represented by the code within the begin and matching end (line 13) will be made active.  I said that in a peculiar fashion because no code is being 'executed', for this does not exist for a CPLD.

So, once we see the CLK signal transition to high, line 8 increments our 'snooze' variable. What does this mean?  It means that the least significant flip-flop in the 19 flip-flops represented by 'snooze' will be toggled, and this may cause carries to ripple up the other flip-flops. Because the CLK signal is transitioning a million times a second, we're incrementing the snooze register one million times a second.

Remember, the whole point of the module is to make the LED blink.  This begins to happen with line 9.  If the value of our register is 500,000,  additional logic should be enabled - the logic between lines 9 and 12.  Since we're using a 1Mhz clock, 500,000 counts represents one half of a second.  This enormous division is required to convert machine-speed into human-speed.

Line 10 shows that our output variable, GO, is inverted.  So if it's 1, the value becomes 0, and vice-versa.  Note that on line 3 we declared GO as 'reg'. This means that, like our 'snooze' counter, GO is persistent; it will retain its value.  Practically speaking the LED attached to GO will stay off or on for 1/2 of a second.

Finally, on line 11, we reset the 'snooze' counter so the process repeats every half a second - we toggle GO off and on, endlessly.

If this were implemented in a high level language, this would be a series of machine instructions.  We all get that.  However, since Verilog configures hardware, the human-consumable output is a schematic, of sorts.  Here's a section of the output relating to the comparison to 500,000:

Here's another snippet showing the least significant 4 bits of the adder produced by line 8 of the Verilog above:

The full schematic is too large to reproduce here.  It's safe to assume, however, it includes perhaps 120 gates.

I entered the Verilog above into the ISE design package provided by Xilinx.  ISE is an easy-to-use software package that includes a Verilog compiler and the related tools.  It produces a binary that can be sent to the CPLD using a JTAG or USB interface.  I use Digilent's 'Coolrunner II Utility Window' software to write the binary to the CPLD.  It's easy and takes about 5 seconds.  Once the writing finishes, the board resets and the new configuration begins running.  Right now the development board is flashing at me dutifully.

In summary, we've learned that Verilog is a common language for configuring CPLDs.  In its simplest form it's very familiar to most programmers.  We've also seen that Verilog produces not executable code, but a gate-level representation suitable for implementation at the hardware level. Finally, we learned that the gate-level implementation is written to the the CPLD is using a USB or JTAG interface.

End of part 2.

In part 3, I'll discuss the control panel.  This will make it easier to understand where this is going.

Wednesday, September 26, 2012

The Electronic Quick Change Gear Box, Part 1

I've posted about my adventures with restoring my 1937 Craftsman 12" lathe.  Today I'll begin something a little different - I'll post about creating an accessory for this lathe to simulate a quick change gearbox (henceforth, QCGB.)

To understand what I am doing, you have to know some basics of lathes.  I'll refer you to Tubalcain, a well regarded instructor. Listen carefully for 'quick change gear box' and 'lead screw.'

One of the neatest capabilities of a lathe is the ability to cut screw threads.  Here's a link to a classic video showing this in action:

Cutting threads

(In that video, the camera is mounted to the carriage.  It looks like the work is moving. It isn't.  The carriage is moving.)

We saw how the lathe cut a screw thread.  But that didn't happen by itself.  What made the cutter find just the right spot to begin?  Why did it cut that rather coarse thread instead of a fine thread?  Why did it cut a thread at all, and not produce a cylinder?

The reason is that the operator configured the lathe so the spindle was connected to the lead screw using a carefully selected gear train. The gear train controlled the ratio of spindle turns to lead screw turns, and by extension the the ratio of spindle revolutions to carriage movement.  If the spindle makes 20 revolutions and the carriage moves 1", a 20 TPI thread will be produced.

In the old days, the ratio between the spindle and lead screw was set by elaborate combinations of individual change gears.  In this picture, the four gears at the bottom (look sharp to see the 4th!) are the change gears.  Those gears were selected from a stack of gears, according to a chart, in order to produce the desired ratio.

So, it takes time to get those gears set up.  Every time you want to move the carriage at a different rate, you need a different change gear setup.

Enter the QCGB

Someone enterprising person realized that if the gears could be engaged as needed, machinists would save a lot of time and thus be more profitable.  The result was the quick change gear box.  While there are many designs and these have evolved over the last century, this QCGB from the Atlas company is representative:

It's simple to use.  We see two levers and a chart.  If you want to cut a certain thread, first find the TPI in the chart.  Note the letter on the left edge of the chart. The left lever is set to the position corresponding to this letter.  Then the right lever is aligned with the column including the desired TPI. That's it. For example, if you wanted to cut a 20 TPI thread, you'd set the left lever to the B position and set the right lever directly under the 3rd column.

Inside, the QCGB isn't so simple.  We see the 'cone' of gears that allows subtle changes to the ratios - 8 to 10 to 12 etc.  On the right we see the gears which divide the spindle revolutions by two.  Each time the move the left lever, this side of the gearbox divides by 2, 4, or 8, etc..  If you look at the chart, you'll notice that the as you move down the chart, the numbers double.

The bad news is that I don't have a QCGB.  If I bought one, it would be quite a project to connect it to my lathe; my lathe was never made to have a QCGB.

What's a computer geek to do!

Perhaps I could just build the QCGB?  Nope - while it would be rewarding, the cost would be prohibitive.  There are probably 25 gears in there and they are very expensive.  Then there's everything else you see.  It adds up fast.

Perhaps I could 'CNC' the lathe - that is, control the carriage movement using a computer.  This requires a computer running dedicated machine control software to be connected to a motor that drives the lead screw.  There's a popular project on the internet called "electronic lead screw" that takes this approach.  I find it unconvincing.  Furthermore, I work with computers every day - I don't want one in the shop.  That's why I have a shop - to get away from computers!

My next idea was to build an electronically assisted QCGB.  Think cut-down CNC with a dedicated computer, tucked out of site.  But this is a lot like the Electronic Lead Screw project and is ultimately just an example of Not Invented Here.  Further, I've heard too many debates about processor speed, issues with non-related jobs running on the computer that induced lag (terrible) and so forth.

I decided to pare the design down to the bare minimum - an electronic device using typical 40xx chips - no programming, no processor, no operating system.  And, as an added benefit, raw speed.

As I was researching the chips I'd need, however, I discovered something remarkable; an IC called a CPLD - Complex Programmable Logic Device.  In this simplest terms, this is a chip with a large number of gates that can be connected together pretty much arbitrarily.  Once connected, it's as if they'd been soldered together by hand.  These amazing devices can allow arbitrary designs tying together hundreds of gates. Best of all, the CPLD can be reprogrammed, thousands of times, using a USB cable and free software.  As if that wasn't enough, a small CPLD can be purchased for a princely $1.25.  The next size up, the one I need, costs $2.50.  I think I can handle it.

Ladies and gentlemen, we have a winner.

To learn about this technology, I purchased a development kit from Digilent that included the following board:

This board includes a pretty thumping CPLD (the Xilinx Coolrunner-II with 256 macrocells), 2 buttons, 2 slide switches, 4 LEDs, and a 4-digit 7-segment LED unit.  All you need to experiment and learn.  The dev kit comes with a USB cable for programming the CPLD and free development software.  So far, it's a 10/10.

Now my goal became clear - implement a full-featured QCGB using a CPLD.

(end of part 1)

In part 2, I'll talk more about the CPLD and what I'm doing with it.